1. Field of the Invention
The present invention relates to encoding problems of test stimulus decompressors in scan-based testing. More specifically, the present invention relates to a circuit for boosting encoding capabilities of test stimulus decompressors.
2. Description of the Related Art
In order to reduce test time and data volume, a stimulus decompressor is inserted on-chip between a tester channels and a scan chain inputs. This enables an on-chip expansion of compressed stimulus into a test pattern to be applied to a chip being tested. The position of the care bits of the test pattern determines whether a particular decompressor is capable of delivering the test pattern intact into the scan chains. If a test pattern test cannot be delivered through the decompressor, it is either replaced by other deliverable patterns or an additional test application phase is employed where the decompressor is bypassed, delivering the pattern without performing compression. Consequently, test quality degrades and test cost increases.
Scan-based testing is widely adopted, in the industry, wherein a large number of scan cells coupled with a large set of scan patterns reflect into inflated test data volume and prolonged test application times. To alleviate the associated costs, test data compression solutions are employed.
Test stimuli compression techniques that are based on the encoding of individual test vectors have been proposed so as to reduce test data volume and possibly test application time. Broadly, the proposed techniques can be categorized as lossless and lossy. Lossless compression techniques deliver perfect test vector encodability by construction. While lossless techniques ensure preservation of fault coverage levels, the stringency of the constraints may impact the compression ratios attained. The lossy test data compression schemes, on the other hand, can still deliver high compression ratios with no test quality degradation by employing an additional phase with no compression or by incorporating Automatic Test Pattern Generation or ATPG into compression.
Some of the lossless test data compression techniques are based on coding schemes. While these techniques can deliver the actual test vectors intact, the indeterminacy in the expansion ratio of the codewords imposes significant synchronization problems. Other lossless compression techniques, such as Linear Feedback Shift Register or LFSR reseeding, have been utilized to deliver fault coverage attained in deterministic tests. In these techniques, a seed transmitted from the tester into the on-chip LFSR is expanded into a test vector to be delivered. To ensure a perfect mapping from LFSR seeds onto every test vector, the LFSR to be utilized on-chip needs to be of a significant size. Techniques such as LFSR seed reordering and a variable number of smaller seed utilization have been proposed to improve LFSR size, test time, and data volume aspects of LFSR reseeding approaches.
Another approach, called SmartBIST, utilizes single input shift registers that drive an XOR network, which in turn feeds internal scan chains. But, the encodability of any pattern is only guaranteed by freezing the internal chains while loading the shift registers in certain cycles. Thus, this approach necessitates the costly implementation of clock gating.
Implementation of the scan architecture in the form of a tree has been another approach for reducing the scan depth, the test time, and data volume. In this technique, all the scan cells in the same level of the tree receive an identical stimulus bit. However, to avoid loss of coverage, the scan cells that are stimulus-compatible need to be placed in the same level of the scan tree. The problem with this approach is that response collection from the scan tree becomes a bottleneck.
Furthermore, such architecture requires that the further away the compatible scan cell group form a scan-in pin, the larger the size of the group. This should result in monotonically increasing sized groups that are levelized from the scan-in pin towards the scan-out pin. But, the architecture fails in real designs, because the size of the compatible scan cell group varies and grouping of scan cells with no regards to scan cell positions is not allowed, due to routing constraints.
Some of the lossy compression techniques are based on limited scan chain access, such as a control of a single chain with deterministically generated test data or the broadcast of the same data into all the scan chains, known as the Illinois scan architecture. Other techniques include the use of a linear decompression network, which can be combinational or sequential. To compensate for the losses, these techniques have to utilize an additional compression-free phase, a test generation, or even include searching for alternative encodable test vectors, because of the missed faults.
Re-configurable fan-out networks, such as a multiplexer-based or switch-based network, have also been used. In these schemes, one of multiple possible parallel broadcast configurations is selected for the application of a test vector by controlling the appropriate select signals. One such architecture offers flexibility in switching from one configuration to another and the delivery of a test vector is accomplished by controlling the appropriate select signals. Another architecture switches from one configuration to another between the shift cycles of the same test vector. However, the problem with each one of these test stimulus compression techniques is that there is a test vector encoding limitation, because these compression techniques do not have the capability of manipulating the care bit distribution.
As has been discussed, the prior art has mostly focused on the design of stimulus decompressors, rather than finding solutions to improve the encodability of decompressors. In fact, the use of stimulus decompressors is de facto in scan-based testing today due to the unbearable cost of testing. These stimulus decompressors can be combinational such as fan-out based, XOR-based, multiplexer-based, or sequential such as phase shifters, LFSRs, etc. Every decompressor has a certain encoding capability, wherein the encodability of a test pattern depends on whether the care bit distribution matches with the structure of the decompressor.
Thus, a circuit method for boosting the encoding capabilities of test stimulus decompressors solving the aforementioned problems is desired.